1. Field of the Invention
The present invention generally relates to a wafer and, more particularly, a wafer having a dicing area and a step region cover with a conductive layer. The present invention also relates to a method of manufacturing therefor.
2. Description of the Background Art
A number of devices or IC chips are formed through wafer processes comprising a pattern forming step comprising thin film formation, pattern exposure and etching, and an impurities forming step comprising ion implantation and heat diffusion and the like. The devices or IC chips are isolated to form individual pellets by a step called dicing. A region for the isolation is called a dicing line or a dicing area. FIG. 1 shows the wafer on which the dicing lines are formed. Referring to FIG. 1, dicing lines DL are formed spaced apart in two directions crossing at right angles on a wafer 1. FIG. 2 is a enlarged sectional view of a region II shown in FIG. 1. Generally, a width W of the dicing areas DL is 50-100.mu.m and a depth D is 3-10.mu.m. Since the dicing area DL is a region cut by a metal rotary blade, an element as an IC (hereinafter referred to as a function element) is not formed in this region, but a test element 30 for testing the function element or an alignment mark 40 for mask alignment is formed.
The test element 30 is formed in the dicing area DL at the same time the function element 20 is formed in a region SA serving as a semiconductor chip. The test element 30 is the same as the function element 20 and it is used to check whether the function element 20 functions normally or not. The test element 30 and the function element 20 are, for example, MOS transistors. An interlayer insulating film 50 is formed on the test element 30. An electrode pad 70 electrically connected to the test element 30 through a wiring layer 60 is formed on the interlayer insulating film 50. It is possible to test the test element 30 by connecting a contact of a tester (not shown) to this electrode pad 70. A MOS semiconductor device having a MOS transistor as an element of a circuit and a check transistor for checking the characteristics of this MOS transistor, which are formed on the same substrate thereof is, for example, disclosed in Japanese Utility Model Laying Open No. 63-100837.
Referring to FIGS. 3A to 3J, a description is given of processes of forming a test element of the background of the present invention. FIGS. 3A to 3J are sectional views taken along a line III-III shown in FIG. 2.
Referring to FIG. 3A, first, isolation oxide films 21 and 22 for electrically isolating elements are formed in semiconductor chip regions SA and test element forming regions TE in dicing areas DL. The isolation oxide film 21 provided in the dicing area DL serves for a test element, and the isolation oxide film 22 provided in the semiconductor chip region SA serves for a function element.
Referring to FIG. 3B, a thin silicon oxide film 31 and 32 used as a gate oxide film is formed on the exposed surface of a semiconductor substrate 1.
Referring to FIG. 3C, a polycrystalline silicon film 4 is formed on the isolation oxide films 21 and 22 and the gate oxide films 31 and 32.
Then, a photoresist film of a positive type, for example, is formed on the polycrystalline silicon film 4. Then, the photoresist film is exposed to light through a mask. Then, by developing the photoresist film, photoresist patterns 51 and 52 shown in FIG. 3C can be obtained. The photoresist patterns 51 and 52 are formed in regions in which gate electrodes are to be formed. Then, a gate electrode 41 for the test element and a gate electrode 42 for the function element shown in FIG. 3D are obtained by etching the polycrystalline silicon film 4, using the photoresist patterns 51 and 52 as a mask.
Referring to FIG. 3E, impurity ions 6 are implanted by an ion implantation method, using the gate electrodes 41 and 42 and the isolation oxide films 21 and 22 as a mask. As a result, impurity diffusion layers 71, 72 and 73 are formed as shown in FIG. 3F. The impurity diffusion layer 71 is a source/drain of the test element, and the impurity diffusion layer 72 is a source/drain of the function element.
Referring to FIG. 3G, an interlayer insulating film 8 is formed on the whole surface of the semiconductor substrate 1. Then, a photoresist film of a positive type, for example, is formed on the interlayer insulating film 8. The photoresist film is exposed to light through a predetermined mask and then developed. As a result, a photoresist pattern 9 is obtained, which extends from the end portions of the gate electrodes 41 and 42 to the isolation oxide films 21 and 22, as shown in FIG. 3G. Then, as shown in FIG. 3H, an interlayer insulating film 81 for the test element and the interlayer insulating film 82 for the function element are obtained by etching the interlayer insulating film 8, using the photoresist pattern 9 as a mask. Contact regions 101 and 102 are formed in the gate electrodes 41 and 42, respectively, in the above described steps.
Then, referring to FIG. 3I, an Al layer 11 is formed by sputtering on the whole major surface of the semiconductor substrate 1 on which the interlayer insulating films 81 and 82 were formed.
Then, a photoresist layer of a positive type, for example, is formed on the Al layer 11. Then, the photoresist layer is exposed to light through a mask. Next, the photoresist layer is developed, whereby an unnecessary portion is removed. As a result, resist patterns 121 and 122 shown in FIG. 3I are formed. The resist patterns 121 and 122 are formed in wiring layer forming regions. Then, anisotropic etching is performed on the Al layer 11 using the photoresist layers 121 and 122 as a mask. As a result of the anisotropic etching, the Al layer 11 is removed except for the portion covered with the photoresist films 121 and 122. However, since the Al layer 11 is formed thick in step portions 80a, 80b, 80c and 80d in the dicing area DL in an etching direction, Al flakes 16 shown in FIG. 3J are not etched away and remain in the step portions 80a to 80d. The step portions 80a and 80d are, here, border portions between the dicing areas DL and the semiconductor chip regions SA, and the step portions 80b and 80c are end portions of the test element forming region TE in the dicing area DL. Then, the photoresist layers 121 and 122 are removed and A1 wiring layers 111 and 112 are obtained. Since the A1 flakes 16 are not securely attached to the step portions 80a to 80d, the Al flakes 16 are prone to come off. If the Al flakes 16 come off to attach to the wiring layer 112 in the semiconductor chip region SA, there is caused a disadvantage that the Al wiring 112 and another wiring layer or the electrode pad short circuit in the semiconductor device. As a result, the yield and reliability in the production of the semiconductor device is reduced.